4‑Bit CPU & Battleship | Project Details

Project Overview

A collaborative digital‑logic project where we designed and bread‑boarded a 4‑bit RISC‑style CPU, wrote a minimal ISA, and built two demo programs—an LED Battleship game and an Fibonacci calculator—entirely in our custom assembly language. The work covered hardware description, micro‑architecture, and low‑level software development.

Architecture Highlights

16‑bit Instruction Word

4‑bit opcode, 3‑bit register fields, 6‑bit immediates.

4 Register File

One hard‑wired to zero, three general purpose.

ALU & Zero‑Flag

Add, sub, and zero‑detect for branching.

Memory‑Mapped I/O

Shared data/I space to drive LEDs & read buttons.

Core Instruction Set

# R‑Type
0000 rd, rs   ; ADD   rd ← rd + rs
0001 rd, rs   ; SUB   rd ← rd – rs

# I‑Type
0010 rd, rs, imm  ; BEQ  if rd == rs PC←PC+imm
0011 rd, imm(rs)  ; LW   rd ← MEM[rs+imm]
0100 rd, imm(rs)  ; SW   MEM[rs+imm] ← rd
0101 rd, imm      ; IN   rd ← IO[imm]
0110 rd, imm      ; OUT  IO[imm] ← rd

# J‑Type
0111 rd           ; JMP  PC ← rd

Assembly Demo – Battleship Snippet

# placeShip: read X/Y buttons, light green LED
LOOP:   in  r1, 0x01      ; read X‑axis button
        in  r2, 0x02      ; read Y‑axis button
        add r3, r1        ; update cursor X
        add r3, r2        ; update cursor Y
        out r3, 0x10      ; move yellow LED
        in  r0, 0x04      ; read ENTER
        beq r0, r0, LOOP  ; if not pressed, loop
        out r3, 0x11      ; fix ship (green)

Key Learnings

Designed full datapath & control in Logisim and wired on breadboard.
Wrote assembler scripts to translate mnemonics → machine code.
Optimised instruction encoding for minimal gate count.
Adapted MIPS conventions to a constrained 4‑register environment.

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